The relentless reduction in the dimensions of semiconductor device features into the deep sub-micron range challenges current fabrication techniques in several respects. It becomes increasingly more difficult to form such ultrafine critical design features with high dimensional accuracy. This problem becomes particularly acute in forming negative features, such as contact holes, via holes, trenches, and microcavities. The minimum size of a feature depends upon the chemical and optical limits of a particular lithography system, and the tolerance for distortions of the shape, such as corner rounding when forming negative features in a layer or substrate. Conventional approaches have included ablation of pattern photoresist, or definition of an inverse pattern to create a hard mask, on which the feature size can be further reduced by means of spacer lithography. These techniques have not proven completely successful or efficient.
Double exposure techniques and spacer lithographic processes have evolved. However, these techniques have not proven completely successful and suffer from low manufacturing throughput, some techniques requiring the repeated use of several tools and chemical mechanical polishing techniques. The competitive marketplace requires a very high throughput, such as yields of 70% and greater, to maintain a profit margin.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor chips comprising devices having accurately formed features in the deep sub-micron range, such as features with a critical dimension less than 20 nm. There exists a particular need for such methodology enabling the accurate formation of ultrafine design features with high efficiency and high manufacturing throughput.